VITA 1:1994 (R2002)
VITA 1:1994 (R2002) Vme64 Covers the main body of the VMEbus specification. Includes both 32 bit and 64 bit usage.
Table of Contents
AbstractForeword
VMEbusSpecificationGeneology
Chapter1
IntroductiontotheVMEbusSpecification
1.1VMEbusSpecificationObjectives
1.2VMEbusInterfaceSystemElements
1.3VMEbusSpecificationDiagrams
1.4SpecificationTerminology
1.5ProtocolSpecification
1.6SystemExamplesandExplanations
Chapter2
DataTransferBus
2.1Introduction
2.2Data-TransferBusLines
2.3DTBModules--BasicDescription
2.4TypicalOperation
2.5Data-TransferBusAcquisition
2.6DTBTimingRulesandObservations
Chapter3
DataTransferBusArbitration
3.1BusArbitrationPhilosophy
3.2ArbitrationBusLines
3.3FunctionalModules
3.4TypicalOperation
3.5RaceConditionsBetweenMasterRequestsandArbiterGrants
Chapter4
PriorityInterruptBus
4.1Introduction
4.2PriorityInterruptBusLines
4.3PriorityInterruptBusModules-BasicDescription
4.4TypicalOperation
4.5RaceConditions
4.6PriorityInterruptBusTimingRulesandObservations
Chapter5
UtilityBus
5.1Introduction
5.2UtilityBusSignalLines
5.3UtilityBusModules
5.4SystemInitializationandDiagnostics
5.5PowerandGroundpins
5.6ReservedLine
5.7AutoSlotId
5.8AutoSystemController
Chapter6
ElectricalSpecifications
6.1Introduction
6.2PowerDistribution
6.3ElectricalSignalCharacteristics
6.4BusDrivingandReceivingRequirements
6.5BackplaneSignalLineInterconnections
6.6UserDefinedSignals
6.7SignalLineDriversandTerminations
Chapter7
MechanicalSpecifications
7.1Introduction
7.2VMEbusBoards
7.3FrontPanels
7.4Backplanes
7.5AssemblyofVMEbusSubracks
7.6ConductionCooledVMEbusSystems
7.7VMEbusBackplaneConnectorsandVMEbusBoardConnectors
AppendixA
GlossaryofVMEbusTerms
AppendixB
VMEbusConnector/PinDescription
AppendixC
Manufacturer'sBoardIdentification
AppendixD
RuleIndex
ListofFigures
1-1SystemElementsDefinedbythisDocument
2-1DataTransferBusFunctionalBlockDiagram
3-1ArbitrationFunctionalBlockDiagram
4-1PriorityInterruptBusFunctionalDiagram
5-1UtilityBusBlockDiagram
6-1VMEbusSignalLevels
7-1SubrackwithMixedBoardSizes
ListofTables
2-1TheEightCategoriesofByteLocations
2-28AddressAlignmentonBus
2-2SignalLevelsDuringDataTransfers
2-3AddressModifierCodes
2-4UseofDataLinestoMoveDataDuringNonmultiplexedData
Transfers
2-29UseoftheAddressandDataLinesforMultiplexedDataCycles
2-5RULESANDPERMISSIONSThatSpecifyTheUseoftheDottedLines
bytheVariousTypesofMasters
2-6Slaves-RULESANDPERMISSIONSThatSpecifytheUseofthe
2-7UseoftheBTO()Mnemonic
2-8LocationMonitors-RULESANDPERMISSIONSThatSpecifytheUse
oftheDottedLinesbytheVariousTypesofLocationMonitors
2-9MnemonicsthatSpecifyAddressingCapabilities
2-10MnemonicsthatSpecifyBasicDataTransferCapabilities
2-11MnemonicsthatSpecifyBlockTransferCapabilities
2-12TheMnemonicthatSpecifiesRead-Modify-WriteCapabilities
2-13Transferring32BitsofDataUsingMultiple-ByteTransferCycles
2-14Transferring16BitsofDataUsingMultiple-ByteTransferCycles
2-15MnemonicthatSpecifiesUnalignedTransferCapability
2-16MnemonicsthatSpecifyAddressonlyCapability
2-30ConfigurationROM/ControlStatusRegisters
2-31ControlandStatusRegisterBaseDefinition
2-32ConfigurationROMDefinition
2-17TimingDiagramsThatDefineMaster,SlaveandLocationMonitor
Operation(seetable2-22fortimingvalues)
2-18DefinitionsofMnemonicsUsedintables2-19,2-20,and2-21
2-19UseoftheAddressandDataLinestoSelectAByteGroup
2-20UseoftheDS1*,DSO*,A1,A2,andLWORD*DuringtheAddress
Phaseofthe
2-21UseoftheDataLinestoTransferData
2-22Master,SlaveandLocationMonitorTimingParameters
2-23Bus-TimerTimingParameters
2-24Master,TimingRULEsandOBSERVATIONS
2-25Slave,TimingRULEsandOBSERVATIONS
2-26LocationMonitor,TimingOBSERVATIONS
2-27BusTimer,TimingRULEs
4-1RULESANDPERMISSIONSthatSpecifytheUseoftheDottedLines
4-2RULESANDPERMISSIONSthatSpecifytheUseoftheDotted
4-3UseoftheIH()MnemonictoSpecifyInterrupt
4-4UseoftheI()MnemonictoSpecifyInterruptRequest
4-5MnemonicsthatSpecifyStatus/IdTransferCapabilities
4-6MnemonicsthatSpecifyInterruptRequestReleaseCapabilities
4-73-BitInterruptAcknowledgeCode
4-8TimingDiagramsthatDefineInterruptHandlerand
4-9TimingDiagramsthatDefineIACKDaisy-ChainDriverOperation
4-10TimingDiagramsthatDefineParticipatingInterrupterOperation
4-11TimingDiagramsthatDefineRespondingInterrupterOperation
4-12DefinitionsofMnemonicsUsedinTables4-13,4-14,and4-15
4-13UseofAddressingLinesDuringInterruptAcknowledgeCycles
4-14UseoftheDS1*,DSO*LWORD*,andWRITELinesDuring
4-15UseofthedatabuslinestotransfertheStatus/Id
4-16InterruptHandler,Interrupter,andIACKDAISY-CHAIN
4-17InterruptHandler,TimingRULESANDOBSERVATIONS
4-18Interrupter,TimingRULESANDOBSERVATIONS
4-19IACKDaisy-ChainDriver,TimingRULESANDOBSERVATIONS
5-1ModuleDriveDuringPower-UpandPower-DownSequences
6-1BusVoltageSpecification
6-2BusDrivingandReceivingRequirements
6-3BusDriverSummary
7-1J1/P1PinAssignments
7-2J2/P2PinAssignments