ESD TR5.3.2-01:2000
ESD TR5.3.2-01:2000 Socket Device Model (sdm) Tester Specifies detailed description of existing SDM test systems and side effects of background tester parasitic RLC transmission line (TL) components.
Table of Contents
1Purpose2TableofContents
3Introduction
4Differencesbetweenan"IdealSocketedCDM"Tester
anda"SocketDeviceModel"Tester
5SocketDeviceModel(SDM)ESDTestSystems
6WhatDoUsersofSDMTestersReallyNeedtoKnow?
6.1WaveformConfirmation
6.2WaveformMeasurementusingDifferentBandwidth
Oscilloscopes
6.3AnExampleofTesterUpgradeInfluenceonTest
Measurements
6.4SDMTesterParasiticCapacitance
6.5DeterminingaDe-ratingFactorwhenAdding
IntermediateBoardsintheDischargePath
7UnderstandingHowAnSDMTestSystemOperates
7.1InternalSDMTesterParasitics
7.2TheEffectofInternalParasiticsonSDM
DischargeWaveforms
7.3TheEffectofDeviceCapacitanceinAnSDMEvent
7.4AnAdditionalNoteaboutInternalICorOn-chip
Capacitance
8WhatDoYouNeedtoKnowtoImproveSDMTesters?
8.1InternalTesterParasitics
8.2TransmissionLineEffects
8.3CapacitiveCouplingduetoHighVoltages
9IdeasRegardingConstructionofNewGeneration
SDMTesters
10Conclusion
11References