ARINC 659:1993

ARINC 659:1993 Backplane Data Bus Defines standards for the transfer of digital data between components within an IMA cabinet. Includes the protocol and timing characteristics for a synchronous backplane data bus capable of transferri

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Table of Contents

1.0INTRODUCTION
1.1PurposeofDocument
1.2DocumentScope
1.3RelationshiptoOtherStandards
1.4ARINCSpecification659BasicPhilosophy
1.5ARINCSpecification659Overview
1.6SupportofARINCReport651
1.7EnvironmentalFactors
1.8SpecificationLanguageandTerminology
1.9RelatedDocuments
2.0TECHNICALDESCRIPTION
2.1BasicArchitecture
2.2PhysicalLayer
2.3DataLinkLayer
2.4DataTypes
2.5TableCompatibility
2.6ErrorManagement
2.7TestandMaintenance
3.0PHYSICALLAYER
3.1Overview
3.2InterfaceSignalDescription
3.3ElectricalPerformanceCharacteristics
3.4TransceiverEnables
3.5BusEncoding
3.6PhysicalSeparation
3.7PassiveTerminator
3.8LRMIdentification
3.9ConnectorPinAssignments
3.10PowerSupplyRouting
3.11BusMedia
4.0DATALINKLAYER
4.1BusOperationOverview
4.2Synchronization
4.3MessageOperation
4.4ReceiveDataSelection
4.5BasicServicesatBIU/HostInterface
ATTACHMENTS
1Glossary
2-1IMACabinetBackplaneArchitecture
2-2Nomenclature
2-3FrameDescriptionLanguage
3-1InterfaceBlockDiagram
3-2InterfaceSignalNames
3-3BackplaneLogicLevels
3-4Set-UpandHoldTiming
3-5Data/ClockSkewMeasurementPoints
3-6SignalOutputTestCircuit
3-7BusEncodingExample
3-8BackplaneTerminatorStructure
3-9InsertPinAssignmentforARINC650
Size1Connector
3.10InsertPinAssignmentforARINC650
Size2Connector
3-11PowerSupplyRouting
4-1BackplaneActivity
4-2WindowDefinitionTaxonomy
4-3InitialFrameDefinition
4-4ExampleFrameOrganization
4-5WindowCommands
4-6BIUStateTransitionDiagram
4-7Full-ResolutionTimeBehavior
4-8VersionRegisterComponents
4-9FrameLevelSynchronizationFlowDiagram
4-10Bit-LevelResyncPulseTimingExample
4-11SpatialSkewMeasurementPoints
4-12TemporalSkewMeasurementPoints
4-13XYSkewMeasurementPoints
4-14TemporalResyncInaccuracyMeasurement
4-15XYResyncInaccuracyMeasurement
4-16Delta(d)TimingConsiderations
4-17Full-ResolutionTimeRegisterComponents
4-18BasicMessageStructure
4-19Master/ShadowMessageStructure
(a)MasterTransmits
(b)Shadow1Transmits
(c)Shadow2Transmits
(d)Shadow3Transmits
4-20InitialSyncMessageStructure
4-21ShortResyncMessageStructure
4-22LongResyncMessageStructure
(a)Master
(b)ThirdShadow
4-23SyncBehaviorforLongResyncMessages
4-24Out_of_SyncBehaviorforLongResyncMessages
4-25DataValidationTables
APPENDICES
ADebugFeatures

Abstract

Defines standards for the transfer of digital data between components within an IMA cabinet. Includes the protocol and timing characteristics for a synchronous backplane data bus capable of transferring data at 60 Mbps using a data path that is two bits wide. The electrical characteristics and behavior expected of the participating modules are defined.

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